Powerful Energy Meter Chipset
ADSST-SALEM-3T
chipset can be interfaced to any general-purpose microproces-
sor to develop state of the art tri-vector or polyphase energy
metering solutions with a wide range of basic currents from 1 A
to 30 A. By incorporating a comprehensive data set of parame-
ters, including instantaneous measurements, accumulated
parameters, and harmonic analysis data, the ADSST-SALEM-3T
chipset meets high end energy metering requirements. The abil-
ity to easily configure the chipset for various parameters makes
it a very flexible solution.
FEATURES
High accuracy
Supports IEC 60687/61036 and ANSI C12.1/12.20
Suitable for class0.5 and class0.2 meter
Full four quadrant measurement of parameters
SPI® compatible serial interface
Pulse output with programmable pulse constant as
pulses/kWh or Wh/pulse
Programmable duty cycle for pulse output
The phase and nonlinearity compensation for current
transformers is done in software (patent pending) without
having to use any passive components in the circuit for
compensation, thus minimizing variations in accuracy with
temperature and time.
Embedded calibration routines for gain and dc offset
Software based phase and nonlinearity compensation for
current transformers
15 kHz sampling frequency
UART mode enables a PC to directly access all computed
parameters
The ADSST-SALEM-3T measures and computes a large num-
ber of parameters essential for high end metering.
Flags to indicate tamper conditions
Single 3.0 V supply
Developer’s kit to accelerate design process (See
Ordering Guide for separate ordering number.)
Table 1.
Parameter
Each Phase
Total
GENERAL DESCRIPTION
RMS Voltage
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
RMS Current
The ADSST-SALEM-3T energy meter chipset consists of an
efficient ADSST-218x digital signal processor (DSP), a fast and
accurate 6-channel, 16-bit ADSST-73360LAR sigma-delta ana-
log-to-digital converter (ADC), and metering software. Two
chipset versions are available to support differing ranges of
operating temperature: The ADSST-EM-3040 chipset is rated at
0°C to 70°C for commercial applications, while the ADSST-EM-
3041 chipset operates at –25°C to +85°C for industrial use.
Active Power
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Apparent Power
Inductive Reactive Power
Capacitive Reactive Power
Power Factor
Frequency
Positive Active Energy
Negative Active Energy
Apparent Energy
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SMPS
LCD DISPLAY
Positive Inductive Reactive Energy
Negative Inductive Reactive Energy
Positive Capacitive Reactive Energy
Negative Capacitive Reactive Energy
SPI BUS
RESISTOR
BLOCK
µC
DSP
ADC
BOOT
FLASH
CT
CT
CT
Voltage Magnitude and Phase for All
Odd Harmonics up to 21st Order
FLASH
OPTO
ꢀ
ꢀ
ꢀ
ꢀ
ADSST-EM-3040
RTC
RS-232
Current Magnitude and Phase for All
Odd Harmonics up to 21st Order
03738-0-001
Figure 1. Block Diagram of a Functional Meter
The ADSST-SALEM-3T offers some excellent features that
make the final meter cost-effective and easy to manufacture.
The ADC and DSP are interfaced to simultaneously acquire
voltage and current samples on all three phases and to perform
mathematically intensive computations to calculate various
instantaneous parameters and perform harmonic analysis. The
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADSST-SALEM-3T
EASY CALIBRATION
EASE OF DESIGN
The ADSST-SALEM-3T chipset has highly advanced calibration
routines embedded into the software. Ease of calibration is the
key feature in this chipset. By sending specific commands to the
ADSST-SALEM-3T chipset, the dc offsets and gains for all volt-
age and current channels can be calibrated automatically. Active
and reactive power calibration is also available for fine-tuning
the errors.
Designing a complete meter using the ADSST-SALEM-3T is
very easy with the ADSST-SALEM-3T-DK developer’s kit. The
kit in the UART mode enables a user to evaluate and test the
computational element by connecting to a PC, without building
the complete hardware.
QUADRANT AND OTHER CONVENTIONS
The metering data computed by the ADSST-SALEM-3T chipset
uses the following conventions for various parameters:
The meter and calibration constants are stored in an external
flash memory, and the lock/unlock calibration feature enables
protection of the calibration constants. The ability to upgrade
the firmware residing in the flash memory makes the meter
adaptable to future needs.
•
Figure 2 gives the quadrant conventions used by the
chipset.
•
•
•
Import means power delivered from the utility to the user.
Export means power delivered by the user to the utility.
Total means total of all three phases.
EFFECTIVE PHASE COMPENSATION
The ADSST-SALEM-3T chipset employs an algorithm (patent
pending) for phase compensation. The ADSST-SALEM-
3T chipset based meter, which is very effective and user friendly,
can be calibrated for phase compensation at three current
points to cover the complete current range. This also reduces
the cost of the end product by reducing the cost of the sensing
elements, i.e., current transformers.
Import and export are with reference to consumption.
U, I:
P:
Magnitude of voltage and current
Active Power (U × I × cos Φ)
Q:
Reactive Power (U × I × sin Φ)
Φ:
Phase angle from the standpoint of I with respect to U,
always positive in counterclockwise direction.
Phase U: L1 = 0° Abs
L2 = 240° Abs
L3 = 120° Abs
ACTIVE EXPORT
ACTIVE IMPORT
REACTIVE
SIN Φ = –1
(–90° Φ)
(90° ABS)
ACTIVE
CAPACITIVE (LEAD)
P–Q– P+Q–
QUADRANT II QUADRANT I
REACTIVE EXPORT
ACTIVE
ACTIVE
COS Φ = –1
COS Φ = +1
Φ
I
(±180° Φ)
(180° ABS)
(0° Φ)
(0° ABS)
I
Q
QUADRANT III QUADRANT IV
P–Q+ P+Q+
REACTIVE IMPORT
ACTIVE
INDUCTIVE (LAG)
REACTIVE
(+90° Φ)
SIN Φ = +1
(270° ABS)
L1, L2, L3
03738-0-002
Figure 2. Quadrant Conventions
Rev. 0 | Page 3 of 24
ADSST-SALEM-3T
This takes place while the processor continues to:
GENERAL DESCRIPTION OF THE ADSST-218X DSP
The ADSST-218x is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
•
•
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal
DMA port
The DSP combines the ADSP-2100 family base architecture
(three computational units, data address generators, and a pro-
gram sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, flag I/O, exten-
sive interrupt capabilities, and on-chip program and data
memory.
•
•
Receive and/or transmit data through the byte DMA port
Decrement timer
ARCHITECTURE OVERVIEW
The ADSST-218x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single proc-
essor cycle. The ADSST-218x assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program
development.
The ADSST-218x is fabricated in a high speed, low power
CMOS process. Every instruction can execute in a single proc-
essor cycle.
The ADSST-218x’s flexible architecture and comprehensive
instruction set enable the processor to perform multiple opera-
tions in parallel. In one processor cycle, the ADSST-218x can:
Figure 3 is the functional block diagram of the ADSST-218x.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations.
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMOR Y
EXTERNAL
ADDRESS
BUS
PROGRAMMABLE
DATA ADDRESS
GENERATORS
PROGRAM
MEMORY
16K × 24-BIT
DATA
MEMORY
16K × 16-BIT
PROGRAM
SEQUENCER
I/O
AND
FLAGS
DAG1 DAG2
EXTERNAL
DATA
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
TIMER
ARITHMETIC UNITS
MAC SHIFTER
SERIAL PORTS
SPORT0
SPORT1
ALU
INTERNAL
DMA
PORT
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
03738-0-008
Figure 3. Functional Block Diagram
Rev. 0 | Page 4 of 24
ADSST-SALEM-3T
Efficient data transfer is achieved with the use of five internal
buses:
The ADSST-218x can respond to 11 interrupts. There are up to
six external interrupts (one edge sensitive, two level sensitive,
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the byte DMA port, and
•
Program Memory Address (PMA) Bus Program Memory
Data (PMD) Bus
RESET
the power-down circuitry. There is also a master
signal.
The two serial ports provide a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes
of operation.
•
•
•
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Serial Ports
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
The ADSST-218x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
BR
control of external buses with bus request/grant signals (
BGH BG0
,
Package Description
, and
). One execution mode (go mode) enables the
The ADSST-218x is available in a 100-lead low profile quad flat
ADSST-218x to continue running from on-chip memory. Nor-
mal execution mode requires the processor to halt while buses
are granted.
Rev. 0 | Page 5 of 24
ADSST-SALEM-3T
ADSST-218X COMMON-MODE PINS
Table 2.
Pin Name
No. of Pins
I/O
O
O
O
I
Function
BG
1
1
1
1
1
1
1
1
1
1
1
1
Bus Grant Output
BGH
BMS
BR
Bus Grant Hung Output
Byte Memory Select Output
Bus Request Input
CMS
DMS
IOMS
PMS
RD
O
O
O
O
O
I
Combined Memory Select Output
Data Memory Select Output
Memory Select Output
Program Memory Select Output
Memory Read Enable Output
Processor Reset Input
RESET
WR
O
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request1
IRQ2/
I
PF7
I/O
I
Programmable I/O Pin
IRQL1/
PF6
1
1
1
1
1
1
1
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
I/O
I
IRQL0/
PF5
Level-Sensitive Interrupt Requests1
I/O
I
Programmable I/O Pin
IRQE/
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
PF4
I/O
I
MODE A
PF0
Mode Select Input−Checked only during RESET
Programmable I/O Pin during Normal Operation
Mode Select Input−Checked only during RESET
Programmable I/O Pin during Normal Operation
Mode Select Input−Checked only during RESET
Programmable I/O Pin during Normal Operation
Mode Select Input−Checked only during RESET
Programmable I/O Pin during Normal Operation
Clock or Quartz Crystal Input
I/O
I
MODE B
PF1
I/O
I
MODE C
PF2
I/O
I
MODE D
PF3
I/O
I
O
CLKIN, XTAL
CLKOUT
EZ-Port
FI, FO
2
1
9
Processor Clock Output
For Emulation Use
Flag In, Flag Out2
I/O
FL0, FL1, FL2
GND
3
10
O
I
Output Flags
Power and Ground
IRQ1:0
PWD
Edge- or Level-Sensitive Interrupts
Power-Down Control Input
1
5
5
1
4
7
2
4
I
SPORT0
SPORT1
PWDACK
VDDEXT
VDDEXT
VDDINT
I/O
I/O
O
I
I
Serial Port I/O Pins
Serial Port I/O Pins
Power-Down Control Output
External VDD (2.5 V or 3.3 V) Power (LQFP)
External VDD (2.5 V or 3.3 V) Power (Mini-BGA)
Internal VDD (2.5 V) Power (LQFP)
Internal VDD (2.5 V) Power (Mini-BGA)
I
I
VDDINT
1Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2SPORT configuration determined by the DSP System Control register. Software configurable.
Rev. 0 | Page 6 of 24
ADSST-SALEM-3T
CLOCK SIGNALS
RESET
Either a crystal or a TTL compatible clock signal can clock the
ADSST-218x.
The
The
signal initiates a master reset of the ADSST-2185x.
signal must be asserted during the power-up
RESET
RESET
sequence to assure proper initialization.
during initial
RESET
power-up must be held long enough to enable the internal clock
to stabilize. If is activated any time after power-up, the
If an external clock is used, it should be a TTL compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL input must be left unconnected.
RESET
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
Because the ADSST-218x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two
are dependent on the crystal type and should be specified by the
crystal manufacturer. A parallel resonant, fundamental
frequency, microprocessor grade crystal should be used.
power-up sequence, the
signal should be held low. On
RESET
any subsequent resets, the
minimum pulse-width specification, tRSP
signal must meet the
RESET
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 autobuffer control register.
.
The input contains some hysteresis; however, if an RC
RESET
circuit is used to generate the
RESET
nal Schmitt trigger is recommended.
signal, the use of an exter-
RECOMMENDED OPERATING CONDITIONS
Table 3.
Parameter
VDDINT
CLKIN
DSP
XTAL
CLKOUT
Min
Max
2.63
3.60
VIH = 3.6
70
Unit
V
V
V
°C
2.37
2.37
VIL = –0.3
0
03738-0-003
VDDEXT
1
VINPUT
Figure 4. External Crystal Connections
TAMB
1The ADSST-2185x is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but
voltage compliance (on output, VOH) depends on the input VDDEXT; because
VOH (MAX) = VDDEXT (MAX). This applies to bidirectional pins (D0–D23, RFS0,
RFS1, SCLK0, SCLK1, TFS0, A1–A13, PF0–PF7) and input only pins (CLKIN,
RESET BR
PWD
,
, DR0, DR1,
).
Rev. 0 | Page 7 of 24
ADSST-SALEM-3T
ADSST-218X ELECTRICAL CHARACTERISTICS
Table 4.
Parameter
Test Conditions
Min
1.5
Typ
Max
Unit
V
VIH High Level Input Voltage1, 2
VIH High Level CLKIN Voltage
VIL Low Level Input Voltage1, 3
VOH High Level Output Voltage1, 4, 5
@ VDDINT = Max
@ VDDINT = Max
2.0
V
@ VDDINT = Min
0.7
V
@ VDDEXT = Min, IOH = –0.5 mA
@ VDDEXT = 3.0 V, IOH = –0.5 mA
@ VDDEXT = Min, IOH = –100 µA6
@ VDDEXT = Min, IOL = 2 mA
2.0
2.4
VDDEXT – 0.3
V
V
V
VOL Low Level Output Voltage1,
IIH High Level Input Current3
IIL Low Level Input Current3
IOZH Three-State Leakage Current7
IOZL Three-State Leakage Current7
IDD Supply Current (Idle)9
0.4
10
10
10
10
V
4,
5
@ VDDINT = Max, VIN = 3.6 V
µA
µA
µA
µA
mA
mA
mA
mA
mA
pF
pF
@ VDDINT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 3.6 V8
@ VDDEXT = Max, VIN = 0 V8
@ VDDINT = 2.5 V, tCK = 15 ns
@ VDDINT = 2.5 V, tCK = 13.3 ns
@ VDDINT = 2.5 V, tCK = 13.3 ns11, TAMB = +25°C
@ VDDINT = 2.5 V, tCK = 15 ns11, TAMB = +25°C
@ VDDINT = 2.5 V, TAMB = +25°C in Lowest Power Mode
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C
9
10
35
38
100
IDD Supply Current (Dynamic)10
IDD Supply Current (Power-Down)12
CI Input Pin Capacitance3, 6
CO Output Pin Capacitance6, 7, 12, 13
8
8
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
RESET BR
PWD
Input only pins:
,
, DR0, DR1,
.
3
RESET BR
, DR0, DR1,
PWD
.
Input only pins: CLKIN,
,
4
BG PMS DMS BMS IOMS CMS RD WR
BGH
.
Output pins:
,
,
,
,
,
,
,
, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0,
5Although specified for TTL outputs, all ADSP-2186 outputs are CMOS compatible and will drive to VDDEXT and GND, assuming no dc loads.
6Guaranteed but not tested.
7
PMS DMS BMS IOMS CMS RD WR
, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
Three-statable pins: A0–A13, D0–D23,
,
,
,
,
,
,
8
BR
.
0 V on
9Idle refers to ADSST-218x state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10
I
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and
DD
Type 6, and 20% are idle instructions.
11
V
= 0 V and 3 V. For typical figures for supply currents, refer to the Power Dissipation section.
IN
12Applies to LQFP package type.
13Output pin capacitance is the capacitive load for any three-stated output pin.
Rev. 0 | Page 8 of 24
ADSST-SALEM-3T
ABSOLUTE MAXIMUM RATINGS—ADSST-218X
Table 5.
Rating
Parameter
Min
Max
Internal Supply Voltage (VDDINT
)
)
–0.3 V
–0.3 V
–0.3 V
–0.5 V
0°C
+3.0 V
+4.0 V
+4.0 V
VDDEXT + 0.5 V
70°C
External Supply Voltage (VDDEXT
Input Voltage1
Output Voltage Swing2
Operating Temperature Range
Storage Temperature Range
–65°C
+150°C
1Applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1,
RESET BR PWD
A1–A13, PF0–PF7) and input-only pins (CLKIN,
,
, DR0, DR1, ).
2
BG PMS DMS BMS IOMS CMS RD WR
Applies to output pins (
,
,
,
,
,
,
,
, PWDACK,
BGH
A0, DT0, DT1, CLKOUT, FL2–FL0,
).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 24
ADSST-SALEM-3T
PIN CONFIGURATION—ADSST-218X
75
74
73
72
71
70
69
68
67
66
65
64
A4/IAD3
A5/IAD4
1
2
D15
D14
PIN 1
IDENTIFIER
3
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
D13
4
D12
5
GND
6
D11
D10
7
8
D9
V
9
DDEXT
10
GND
11
12
D8
D7/IWR
ADSST-218x
63 D6/IRD
13
14
15
16
17
18
19
CLKIN
TOP VIEW
(Not to Scale)
62
61
60
59
58
D5/IAL
D4/IS
GND
XTAL
V
DDEXT
CLKOUT
GND
V
DDINT
D3/IACK
V
DDINT
57 D2/IAD15
WR
D1/IAD14
D0/IAD13
BG
RD 20
56
55
54
53
52
51
21
22
BMS
DMS
PMS 23
EBG
24
25
IOMS
CMS
BR
EBR
03738-0-009
Figure 5. Pin Configuration for ADSST-218x in 100-Lead LQFP
Rev. 0 | Page 10 of 24
ADSST-SALEM-3T
The ADSST-73360LAR is particularly suitable for industrial
power metering as each channel samples synchronously, ensur-
ing that there is no (phase) delay between the conversions. The
ADSST-73360LAR also features low group delay conversions on
all channels.
GENERAL DESCRIPTION OF THE ADSST-73360LAR
ADC
The ADSST-73360LAR is a 6-channel input analog front end
processor for general-purpose applications, including industrial
power metering or multichannel analog inputs. It features six
16-bit A/D conversion channels, each of which provides 76 dB
signal-to-noise ratio over a dc to 4 kHz signal bandwidth. Each
channel also features an input programmable gain amplifier
(PGA) with gain settings in eight stages from 0 dB to 38 dB.
An on-chip reference voltage is included with a nominal value
of 1.2 V.
The ADSST-73360LAR is available in a 28-lead SOIC package.
VINP1
SIGNAL
Σ-∆
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
DECIMATOR
DECIMATOR
DECIMATOR
SDI
VINN1
SDIFS
SCLK
VINP2
VINN2
VINP3
SIGNAL
Σ-∆
SIGNAL
CONDITIONING
0/38DB
PGA
CONDITIONING
SIGNAL
Σ-∆
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
VINN3
RESET
MCLK
SE
SERIAL
I/O
PORT
REFCAP
REFOUT
REFERENCE
ADSST-73360LAR
VINP4
VINN4
SIGNAL
Σ-∆
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
DECIMATOR
DECIMATOR
VINP5
VINN5
VINP6
VINN6
SIGNAL
Σ-∆
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
SDO
SDOFS
SIGNAL
Σ-∆
CONDITIONING
SIGNAL
CONDITIONING
0/38DB
PGA
DECIMATOR
03738-0-004
Figure 6. ADSST-73360LAR Functional Block Diagram
Rev. 0 | Page 11 of 24
ADSST-SALEM-3T
SPECIFICATIONS—ADSST-73360LAR
(AVDD = 2.7 V to 3.6 V, DVDD = 2.7 V to 3.6 V, DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz, fS = 8 kHz, TA = TMIN to
TMAX1, unless otherwise noted.)
Table 6.
Parameter
REFERENCE
REFCAP
Min
Typ
Max
Unit
Test Conditions
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
1.08
1.2
50
1.32
V
ppm/°C
0.1 µF Capacitor Required from REFCAP to AGND2
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
ADC SPECIFICATIONS
130
1.2
Ω
V
kΩ
pF
1.08
1
1.32
100
Unloaded
Maximum Input Range at VIN2, 3
1.578
–2.85
1.0954
V p-p
dBm
V p-p
Measured Differentially
Measured Differentially
Nominal Reference Level at VIN
(0 dBm0)
–6.02
dBm
Absolute Gain
PGA = 0 dB
PGA = 38 dB
–1.3
–0.8
+0.6
+0.8
dB
dB
1.0 kHz
1.0 kHz
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 0 dB
76
76
dB
dB
0 Hz to 4 kHz; fS = 8 kHz
0 Hz to 2 kHz; fS = 8 kHz
fIN = 60 kHz
71
PGA = 38 dB
58
dB
0 Hz to 4 kHz; fS = 64 kHz
Total Harmonic Distortion
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk ADC-to-ADC
DC Offset
–80
–64
–78
–68
–95
–71
+30
dB
dB
dB
dB
dB
mV
dB
0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 kHz
0 Hz to 2 kHz; fS = 64 kHz; fIN = 60 kHz
PGA = 0 dB
PGA = 0 dB, fS = 64 kHz; SCLK = 16 MHz
ADC1 at Idle; ADC2 to ADC6 Input Signal: 60 Hz
PGA = 0 dB
–30
Power Supply Rejection
–55
Input Signal Level at AVDD and DVDD Pins
1.0 kHz, 100 mV p-p Sine Wave
Group Delay4, 5
25
64 kHz Output Sample Rate
32 kHz Output Sample Rate
16 kHz Output Sample Rate
8 kHz Output Sample Rate
DMCLK = 16.384 MHz
µs
50
µs
µs
95
190
25
0.15
0.01
µs
kΩ6
Input Resistance at VIN2, 4
Phase Mismatch
Degrees fIN = 1 kHz
Degrees fIN = 60 Hz
Rev. 0 | Page 12 of 24
ADSST-SALEM-3T
Parameter
Min
Typ
Max
Unit
Test Conditions
FREQUENCY RESPONSE
(ADC)7 Typical Output Frequency
(Normalized to fS)
0
0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
> 0.5
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
LOGIC OUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD – 0.8
0
VDD
0.8
10
V
V
µA
pF
10
VDD – 0.4
VDD
0.4
V
|IOUT| ≤ 100 µA
0
V
|IOUT| ≤ 100 µA
–10
+10
µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
2.7
2.7
3.6
3.6
V
V
IDD8
See Table 7
1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Frequency response of the ADC measured with input at audio reference level (the input level that produces an output level of 0 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.
Table 7. Current Summary (AVDD = DVDD = 3.3 V)
Digital Current,
Max (mA)
Conditions
SE
1
MCLK ON
Yes
Comments
ADCs Only On
25
REFOUT Disabled
REFOUT Disabled
REFCAP Only On
REFCAP and REFOUT Only On
All Sections On
1.0
0
No
3.5
0
No
26.5
1.0
1
Yes
REFOUT Enabled
All Sections Off
1
Yes
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
All Sections Off
0.05
0
No
The above values are in mA and are typical values, unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
Rev. 0 | Page 13 of 24
ADSST-SALEM-3T
ABSOLUTE MAXIMUM RATINGS—ADSST-73360LAR
(TA = 25°C unless otherwise noted)
Table 8.
Parameter
Rating
AVDD, DVDD to GND
AGND to DGND
–0.3 V to +4.6 V
–0.3 V to +0.3 V
–0.3 V to DVDD + 0.3 V
–0.3 V to AVDD
0°C to +70°C
–65°C to +150°C
150°C
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Thermal Impedance θJA (SOIC)
75°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 14 of 24
ADSST-SALEM-3T
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS—ADSST-73360LAR
VINP2
VINN2
1
2
3
4
5
6
7
8
9
28 VINN3
27 VINP3
26 VINN4
25 VINP4
24 VINN5
23 VINP5
22 VINN6
21 VINP6
20 AVDD1
19 AGND1
18 SE
VINP1
TOP VIEW
(Not to Scale)
VINN1
REFOUT
REFCAP
AVDD2
AGND2
DGND
DVDD 10
RESET 11
SCLK 12
MCLK 13
SDO 14
17 SDI
16 SDIFS
15 SDOFS
NC = NO CONNECT
03738-0-005
Figure 7. ADSST-73360LAR Pin Configuration—RW-28
PIN FUNCTION DESCRIPTIONS
Table 9.
Pin No.
Mnemonic
VINP2
VINN2
VINP1
VINN1
Function
1
2
3
4
5
6
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.
REFOUT
REFCAP
Reference Voltage for ADCs. A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip
reference. The capacitor should be fixed to this pin. The internal reference can be overdriven
by an external reference connected to this pin if required.
7
8
9
10
11
AVDD2
AGND2
DGND
DVDD
RESET
Analog Power Supply Connection.
Analog Ground/Substrate Connection.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low Reset Signal. This input resets the entire chip, resetting the control registers and
clearing the digital circuitry.
12
SCLK
Output Serial Clock whose rate determines the serial transfer rate to/from the ADSST-
73360LAR. It is used to clock data or control information to and from the serial port (SPORT).
The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an
integer number that is the product of the external master clock rate divider and the serial
clock rate divider.
13
14
MCLK
SDO
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the ADSST-73360LAR. Both data and control information may be output
on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no
information is being transmitted and when SE is low.
15
16
17
SDOFS
SDIFS
SDI
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active
one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the
positive edge of SCLK. SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative
edge of SCLK and is ignored when SE is low.
Serial Data Input of the ADSST-73360LAR. Both data and control information may be input on
this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low.
Rev. 0 | Page 15 of 24
ADSST-SALEM-3T
Pin No.
Mnemonic
Function
18
SE
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP,
the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also
disabled internally in order to decrease power dissipation. When SE is brought high, the
control and data registers of the SPORT are at their original values (before SE was brought
low); however, the timing counters and other internal registers are at their reset values.
19
20
21
22
23
24
25
26
27
28
AGND1
AVDD1
VINP6
VINN6
VINP5
VINN5
VINP4
VINN4
VINP3
VINN3
Analog Ground Connection.
Analog Power Supply Connection.
Analog Input to the Positive Terminal of Input Channel 6.
Analog Input to the Negative Terminal of Input Channel 6.
Analog Input to the Positive Terminal of Input Channel 5.
Analog Input to the Negative Terminal of Input Channel 5.
Analog Input to the Positive Terminal of Input Channel 4.
Analog Input to the Negative Terminal of Input Channel 4.
Analog Input to the Positive Terminal of Input Channel 3.
Analog Input to the Negative Terminal of Input Channel 3.
A minimum etch technique is generally best for ground planes
as it gives the best shielding. Digital and analog ground planes
should be joined in only one place. If this connection is close to
the device, it is recommended to use a ferrite bead inductor as
shown in Figure 9.
GROUNDING AND LAYOUT
Since the analog inputs to the ADSST-73360LAR are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode
rejection of the part will remove common-mode noise on these
inputs. The analog and digital supplies of the ADSST-73360LAR
are independent and separately pinned out to minimize
coupling between analog and digital sections of the device. The
digital filters on the encoder section provide rejection of
broadband noise on the power supplies, except at integer
multiples of the modulator sampling frequency. The digital
filters also remove noise from the analog inputs, provided the
source does not saturate the analog modulator. However,
because the resolution of the ADSST-73360LAR’s ADC is high
and the noise levels from the ADSST-73360LAR are so low, care
must be taken with regard to grounding and layout.
Avoid running digital lines under the device for they will couple
noise onto the die. The analog ground plane should be enabled
to run under the ADSST-73360LAR to avoid noise coupling.
The power supply lines to the ADSST-73360LAR should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply lines. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board,
and clock signals should never be run near the analog inputs.
Traces on opposite sides of the board should run at right angles
to each other. This will reduce the effects of feed-through
through the board. A microstrip technique is by far the best but
is not always possible with a double-sided board. In this tech-
nique, the component side of the board is dedicated to ground
planes while signals are placed on the other side.
The printed circuit board that houses the ADSST-73360LAR
should be designed in such a way that the analog and digital
sections are separated and confined to certain sections of the
board. The ADSST-73360LAR pin configuration offers a major
advantage in that its analog and digital interfaces are connected
on opposite sides of the package. This facilitates the use of
ground planes that can be easily separated, as shown in Figure 8.
Good decoupling is important when using high speed devices.
All analog and digital supplies should be decoupled to AGND
and DGND, respectively, with 0.1 µF ceramic capacitors in
parallel with 10 µF tantalum capacitors. To achieve the best
from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against it. In systems
where a common supply voltage is used to drive both the
AVDD and DVDD of the ADSST-73360LAR, it is
ANALOG GROUND
recommended that the system’s AVDD supply be used. This
supply should have the recommended analog supply decoupling
between the AVDD pins of the ADSST-73360LAR and AGND,
and the recommended digital supply decoupling capacitors
between the DVDD pin and DGND.
DIGITAL GROUND
03738-0-006
Figure 8. Ground Plane Layout
Rev. 0 | Page 16 of 24
ADSST-SALEM-3T
The ADSST-73360LAR has a peak-to-peak input range of VREF
–
POWER-UP INITIALIZATION AND DATA FROM THE
ADSST-SALEM-3T
(VREF × 0.6525) to VREF + (VREF × 0.6525); for VREF = 2.5 V, this is
0.856 V to 4.14 V p-p. This limit defines the resistance network
on the potential circuits and the burden resistance on the sec-
ondary side of the CT. Since the ADSST-73360LAR is a unipolar
ADC, the ac potential and current signals have to be offset by
some dc level. The reference design has a dc offset of 2.5 V. This
limits the peak-to-peak signal range of potential and current to
3.28 V p-p or 1.16 V rms.
The ADSST-SALEM-3T-EV boot loads the code from the
nonvolatile flash memory as shown in the block diagram of
tion data also gets loaded from the nonvolatile memory. For
further details on boot loading, refer to the ADSST-SALEM-3T-
DK (Developer’s Kit) User Manual. The user manual also
describes various commands for instantaneous and computed
parameters.
Potential Section
The selection of the potential divider circuit should be such that
it can:
VOLTAGE AND CURRENT SENSING
Figure 9 shows the input section for the voltage and current
sections. Based on the voltage and current values, the GUI
software in the ADSST-SALEM-3T-DK computes the values of
resistors R1, R2, and R3. The closest available values to those
calculated by the GUI software should be selected and used.
• Handle high surge voltages
• Have minimum VA burden
• Give approximately 1 V peak headroom to accommodate
overvoltages.
VOLTAGE INPUT
PHASE
VOLTAGE
Current Section
R1
TO ADC
CHANNEL
The selection of CT ratio and burden resistance should be such
that it can:
R2
NEUTRAL
• Handle the complete dynamic range for the current signal
input.
CURRENT INPUT
TO ADC
CHANNEL
• Give approximately 1 V peak headroom to accommodate
PHASE
R3
loads with high crest factors.
CURRENT
NEUTRAL
03738-0-007
The reference design has a CT with a turns ratio of 1:2500 and
burden resistance of 82 Ω. This generates 0.656 V rms or
0.928 V peak at 20 A current. This leaves enough margin for
current pulses or low crest factor loads, such as SMPS. The
maximum current can be up to 32.768 A.
Figure 9. Input Section
Rev. 0 | Page 17 of 24
ADSST-SALEM-3T
ACCURACY OF REFERENCE DESIGN USING THE ADSST-SALEM-3T CHIPSET
Overall Accuracy, Power, and Energy Measurement
The accuracy figures are measured under typical specified conditions, unless otherwise indicated.
Table 10. Test Conditions for Reference Design Using a µ Metal CT of Class 0.5 Accuracy
Parameter
Nominal Value
VN = 230 V 1%
300 V
Nominal Voltage (Phase to Neutral) VN
Maximum Voltage (Phase to Neutral)
Nominal Current
IN = 5 A
Maximum Current IMAX
Frequency
Temperature
IMAX = 20 A
FN = 50 Hz/60 Hz 10%
23 2°C
Table 11. Maximum Error (Power and Energies)
Current
Voltage
PF
Min
Typ
Max
±0.2
±0.2
±0.35
±0.35
±0.2
±0.2
Unit
%
VN
VN
VN
1.0
0.01 IN ≤ I < 0.05 IN
0.05 IN ≤ I < IMAX
0.02 IN ≤ I< 0.1 IN
±0.1
±0.1
±0.15
±0.15
±0.1
±0.1
1.0
%
0.5 Lagging
0.8 Leading
0.5 Lagging
0.8 Leading
%
%
VN
%
0.05 IN ≤ I < IMAX
%
Table 12. Unbalanced Load Error
Current
Voltage
PF
Min
Min
Min
Typ
Max
±0.2
±0.2
Unit
%
VN
VN
1.0
0.05 IN ≤ I ≤ IMAX
±0.15
±0.15
0.5 Lagging
%
0.1 IN ≤ I ≤ IMAX
Table 13. Voltage Variation Error
Voltage
VN ± 10%
VN ± 10%
Current
PF
Typ
Max
±0.1
±0.1
Unit
%
1.0
0.05 IN ≤ I ≤ IMAX
±0.05
±0.05
0.5 Lagging
%
0.1 IN ≤ I ≤ IMAX
Table 14. Frequency Variation Errors
Frequency
Current
PF
Typ
Max
±0.1
±0.1
Unit
%
1.0
fN ± 10%
0.05 IN ≤ I ≤ IMAX
±0.05
±0.05
0.5 Lagging
%
fN ± 10%
0.1 IN ≤ I ≤ IMAX
Table 15. Harmonic Distortion Error
Current
Current
Min
Min
Typ
Max
Unit
10% of 3rd Harmonic
%
0.05 IN ≤ I ≤ IMAX
±0.05
±0.1
Table 16. Reverse Phase Sequence Error
Current
Voltage
Typ
Max
Unit
0.1 IN
VN
%
±0.05
Rev. 0 | Page 18 of 24
ADSST-SALEM-3T
Table 17. Voltage Unbalance Error
Current
Voltage
Min
Typ
Max
Unit
IN
VN + 15% V
%
±0.1
±0.2
Table 18. Starting Current
Min
Typ
Max
Unit
0.07
0.1
% of IN
Rev. 0 | Page 19 of 24
ADSST-SALEM-3T
OUTLINE DIMENSIONS
16.00 BSC SQ
14.00 BSC SQ
1.60 MAX
100
1
76
75
0.75
0.60
0.45
12°
TYP
PIN 1
SEATING
PLANE
12.00
REF
TOP VIEW
(PINS DOWN)
10°
6°
2°
1.45
1.40
1.35
0.20
0.09
VIEW A
7°
3.5°
0°
25
51
50
26
0.50 BSC
0.15
0.05
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BED
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
18.10 (0.7126)
17.70 (0.6969)
28
1
15
14
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
0.25 (0.0098)
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
1.27 (0.0500)
BSC
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 11. 28-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
Rev. 0 | Page 20 of 24
ADSST-SALEM-3T
ORDERING GUIDE
Part Number1
Temperature Range
Processors Included
ADSST-2185MKST-300
ADSST-73360LAR
Package
ADSST-EM-3040
0°C to +70°C
ST-100
RW-28
ST-100
RW-28
ADSST-EM-3041
−25°C to +85°C
ADSST-2185MBST-266
ADSST-73360LAR
1
For developer’s kit, order ADSST-SALEM-3T-DK.
Rev. 0 | Page 21 of 24
ADSST-SALEM-3T
NOTES
Rev. 0 | Page 22 of 24
ADSST-SALEM-3T
NOTES
Rev. 0 | Page 23 of 24
ADSST-SALEM-3T
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
D03738–0–7/04(0)
Rev. 0 | Page 24 of 24
|